At-Speed Distributed Functional Testing to Detect Logic and Delay

PDF] At-Speed Distributed Functional Testing to Detect Logic and

At-speed scan testing with LOC scheme.

PDF] At-Speed Distributed Functional Testing to Detect Logic and

Delay Faults

PDF] A Scalable built-in self-test/self-diagnosis architecture for 2D-mesh based chip multiprocessor systems

Efficient Design-for-Test Approach for Networks-on-Chip

Transmission Line Termination Techniques in High Speed Design

Techniques to Measure and Avoid Jitter in PCBs

PDF) A Cost-Effective Scheme for Network-on-Chip Router and Interconnect Testing

Screening For Silent Data Errors

Client Server Testing What it is, Advantages & Challenges

Handshaking protocol Fig 1 shows data and control connections for a

Detection and Localization of Channel-Short Faults in Regular On-Chip Interconnection Networks

Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks